A programmable logic device (PLD) is a general-purpose device that can be programmed by a user to implement a variety of selected functions. One type of PLD is the Field Programmable Gate Array (FPGA), which typically includes an array of configurable logic blocks (CLBs) surrounded by a plurality of input/output blocks (IOBs). The CLBs are individually programmable and can be configured to perform a variety of logic functions on a few input signals. The IOBs can be configured to drive output signals from the CLBs to external pins of the FPGA and/or to receive input signals from the external FPGA pins. The FPGA also includes a programmable interconnect structure that can be programmed to selectively route signals among the various CLBs and IOBs to produce more complex functions of many input signals. The CLBs, IOBs, and the programmable interconnect structure are programmed by loading configuration data into associated configuration memory cells that control various switches and multiplexers within the CLBs, IOBs, and the interconnect structure to implement logic and routing functions specified by the configuration data.
PLDs such as FPGA devices typically exhibit greater static power consumption than dedicated logic devices such as standard-cell application specific integrated circuits (ASICs). One reason for the PLD's high power consumption is because while the PLD utilizes only a subset of its available resources for any given design, the unused resources nevertheless consume static power. As a result, PLDs are sometimes not suitable for low-power applications such as, for example, portable devices. Further, as known in the art, core logic elements such as the CLBs and embedded memory elements such as Block RAM and the configuration memory cells of a PLD may account for a significant portion of the PLD's static power consumption. Indeed, leakage currents associated with volatile memory elements such as DRAM cells and/or SRAM cells consume static power even when not actively used by the PLD. Similarly, leakage currents associated with the PLD's core logic elements consume static power even when not actively used by the PLD.
One technique to reduce power consumption when the PLD is not being actively used (during a standby mode) is to remove power from the PLD and thereby power-down the PLD's various components. Although effective in minimizing static power consumption during standby mode, powering-down various PLD various components such as the configuration memory cells causes data stored therein to be lost, and therefore requires the PLD to be re-configured (e.g., from an external memory) prior to subsequent use.
Therefore, there is a need for a PLD to implement more effective power reduction techniques during standby mode.